1. Field of the Invention
The present invention relates to a testing protocol for a semiconductor device. More particularly, the invention relates to a testing protocol implemented by real-time optimized test program(s) for a semiconductor device and an automated test method using same.
This application claims the benefit of Korean Patent Application No. 10-2006-0060662, filed on Jun. 30, 2006, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
Contemporary semiconductor devices are fabricated using an extremely complex sequence of processes. The proper application of these processes as well as the functionality provided by the circuitry formed on semiconductor devices must be systematically verified by numerous sophisticated testing protocols. Functional testing is performed on semiconductor devices on the wafer level, the module level, and package level. In order to provide the necessary efficiency, much of this testing is performed by automatic testing systems using a group of specialized equipment platforms, each generically referred to hereafter as “a tester.”
Despite considerable efforts to detect and address problems with semiconductor devices at the wafer level, some latent problems with the functionality of semiconductor devices are only detected once the individual semiconductor dies are packaged by downstream manufacturers. Further, despite testing the additional testing performed by packaging manufacturers some latent quality problems are only detected by consumers of the semiconductor devices, such as end users, retailers, and electronic system or consumer products manufacturers.
Quality problems noted by consumers are highly undesirable for the manufacturer of semiconductor devices and can lead to expensive replacement or repair programs. As a result, semiconductor device manufacturers have expanded and enhanced electrical test programs for semiconductor devices in order to eliminate the possibility of quality programs impacting consumers. Unfortunately, the expansion and enhancement of the electrical test programs lengthens test periods for semiconductor devices.
Indeed, a testing overkill phenomenon may occur. Testing overkill may actually result in the disqualification of acceptable semiconductor devices. Production yields may be unnecessarily impacted and profit margins eroded. Thus, a difficult balance must be struck between adequate testing of semiconductor devices—which is sufficient to identify quality problems, and over-testing of semiconductor devices—which unjustifiably extends testing time and unnecessarily reduces production yields.
Achieving this testing balance requires an iterative engineering approach of running certain tests, analyzing the test results, and modifying the tests in view of the testing results. However, this iterative test development is a lengthy and resource intensive process as engineers must manually edit the automated tests, edit the software programs implementing the tests, compile the edited test programs to implement the programs in execution files, and install the execution files into the automated testing equipment. This conventional approach to the refinement of testing protocols is slow and not well adapted to quickly addressing newly identified quality problems.